Field of the Invention .Iaddend.
The invention relates to an integrated semiconductor memory, having memory cells disposed in matrix form in a memory cell field, which are triggerable through word lines and internal bit lines forming pairs of internal bit lines, one internal weighting circuit per internal bit line pair, one pair of separation transistors per internal bit line pair for the electrical separation of the internal bit line pair from an external pair of bit lines that are common to the internal bit Lines, a bit line decoder for triggering the pairs of separation transistors, an external weighting circuit, and a discriminator device and a precharging device which are connected to the external bit line pair.
Modern integrated semiconductor memories contain a great number of memory cells. For instance, modern DRAMs have a memory capacity of 4 or 16 megabits. The testing time for typical function tests is known to increase linearly at least twice as fast as the number of memory cells increases. Many test patterns in fact produce a quadratic increase in testing time as memory capacity increases. Attempts have therefore already been made for some time to provide devices in the semiconductor memory itself that make it possible to shorten the testing time. For instance, that can be attained by operating a plurality of memory cells (which operate independently of one another in normal operation) parallel to one another in the test mode, ascertaining the outcome of testing internally in the memory, and finally making the results available as an error signal at the usual data output terminal.
A circuit configuration of that generic type is known, for instance, from Published European Application 0 283 907 A1 corresponding to U.S. Pat. No. 4,956,819. That device enables a simultaneous readout of (test) data from all of the memory cells disposed along one word line. Such a memory can accordingly be tested parallel, line by line. There are two disadvantageous aspects of the known circuit configuration: First, for the test mode, a potential that is quantitatively between the two typical supply potentials of the semiconductor memory must be furnished to trigger the separation transistors. That requires an independent generation of potential on the semiconductor chip itself. Second, in the test mode, it may happen that if an error occurs in one memory cell in a single word line, the internal weighting circuit assigned to the memory cell, after an initially correct weighting, will incorrectly flip into a state that indicates that the (actually defective) memory cell is functioning properly. One way in which that may happen, if the potential at the gate of the separation transistors is dimensioned disadvantageously, is that the (correct) data, which are read out from the other memory cells on the same word line and naturally reach the external bit line in the form of electrical potential over their internal bit lines and thus also reach the bit line connected to the defective memory cell, may pull or push this bit line to a potential that causes the internal weighting circuit to flip. Thus the internal weighting circuit flips from the state that originally correctly indicated the defective memory cell to a state that is meant to indicate a "good" cell.
It is accordingly an object of the invention to provide an integrated semi-conductor memory, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and which des so in such a way that the aforementioned error cannot occur.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor memory, comprising a memory cell field having memory cells disposed in matrix form, word lines and internal bit lines forming pairs of internal bit lines for triggering the memory cells, internal weighting circuits each being assigned to a respective one of the internal bit line pairs, an external pair of bit lines being commonly assigned to the internal bit lines, pairs of separation transistors each being assigned to a respective one of the internal bit line pairs for electrical separation of the respective internal bit line pair from the external pair of bit lines, a bit line decoder for triggering the pairs of separation transistors, an external weighting circuit, a discriminator device and a precharging device connected to the external bit line pair, means for triggering the internal bit lines of each pair of internal bit lines separately from one another, and means for connecting the internal bit lines of each pair of internal bit lines to the external bit line pair separately from one another.
In accordance with another feature of the invention, the separate triggering means are part of the bit line decoder and operate as a function of a pair of test signals.
In accordance with a further feature of the invention, the bit line decoder has a decoder line, and the separate triggering means include a pair of series-connected switch transistors having sources connected in common to the decoder line, drains connected to gates of the separation transistors, and gates connected to the pair of test signals, for separate triggering of the pairs of separation transistors.
In accordance with an added feature of the invention, the separation transistors are first separation transistors, the separate triggering means trigger the transistors of each pair of first separation transistors in parallel with one another, and there are provided pairs of second separation transistors each being assigned to a respective one of the pairs of first separation transistors for separate triggering of the internal bit lines of each pair of internal bit lines, each of the first separation transistors being connected in series with a respective one of the second separation transistors, and in each pair of second separation transistors, one transistor being controlled by a first test signal and the other transistor being controlled by a second test signal.
In accordance with an additional feature of the invention, the pairs of second separation transistors are disposed between the memory cell field and the pairs of first separation transistors.
In accordance with yet another feature of the invention, the pairs of second separation transistors are disposed between the external bit line pair and the pairs of first separation transistors.
In accordance with yet a further feature of the invention, there is provided a common diffusion zone acting as respective source and drain zones for a transistor of a pair of second separation transistors and one transistor of a pair of first separation transistors connected thereto.
In accordance with yet an added feature of the invention, there are provided conductor tracks of the external bit line pair, and conductor tracks carrying the test signals and shielding with respect to the conductor tracks of the external bit line pair.
In accordance with a concomitant feature of the invention, in a test mode, one of the bit lines of the external bit line pair is precharged to logical 1, and the other of the bit lines of the external bit line pair is precharged to a potential being lower than the value of logical 1 by half an amount by which the one bit line of the external bit line path precharged to logical 1 drops in the case of error.
Other features which are considered as characteristic for the insertion are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated semiconductor memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scone and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.